A typical electronic image sensor comprises a number of light sensitive picture elements (“pixels”) arranged in a two-dimensional array. Such an image sensor may be configured to produce a color image by forming an appropriate color filter array (CFA) over the pixels. Examples of image sensors of this type are disclosed in United States Patent Application Publication 2007/0024931, entitled “Image Sensor with Improved Light Sensitivity,” which is incorporated by reference herein.
As is well known, an image sensor may be implemented using complementary metal-oxide-semiconductor (CMOS) circuitry. In such an arrangement, each pixel typically comprises a photodiode and a number of transistors. The pixel transistors may be p-type MOS (PMOS) transistors, in which case the photodiode and the transistors are generally formed in an n-well region on a p-type substrate. Alternatively, the pixel transistors may be n-type MOS (NMOS) transistors, in which case the photodiode and the transistors are generally formed in a p-well region on an n-type substrate.
“Well bounce” is a problem that arises in CMOS image sensors having pixels formed in n-well or p-well regions of the type described above. Well bounce is an undesirable variation in well voltage that is typically due to the well bias voltage being introduced through well contacts in a ring around the periphery of the pixel array. These well contacts are close to edge pixels of the array but far from central pixels of the array. As a result, the resistance of the well from the edge of the array to its center can be very large, causing well bounce to occur in conjunction with switching operations associated with pixel sampling and readout.
A number of techniques have been developed in an attempt to alleviate the well bounce problem. One such technique involves increasing well conductivity, as described in, for example, U.S. Pat. No. 6,271,554, entitled “Solid-State Image Sensor Having a Substrate with an Impurity Concentration Gradient.” However, an approach of this type requires process changes, which can increase manufacturing cost and complexity, and in any event may not provide a sufficient reduction in well bounce.
Another technique involves the addition of well contacts within the pixel array, as described in, for example, U.S. Pat. No. 7,016,089, entitled “Amplification-Type Solid State Imaging Device with Reduced Shading” or U.S. Pat. No. 7,485,903, entitled “Solid State Imaging Device.” Unfortunately, the additional well contacts within the pixel array consume limited area that can otherwise be used for the photodiodes, and thus adversely impact the performance of the image sensor. Contacts within the pixel array also adversely effects pixel dark current as documented by U.S. Pat. No. 7,456,880, entitled “Photoelectric Conversion Element Having a Plurality of Semiconductor Regions and Including Conductive Layers Provided on Each Isolation Element Region.”
A further technique involves reducing the clock speed for certain signals associated with sampling and readout of the pixels. See, for example, U.S. Pat. No. 7,468,750, entitled “Solid-State Imaging Device Having Transition Time Relationship for Drive Signals.” However, slower clocking means it will take longer to read out the pixel data associated with a given image.